Recent Changes in ATLAS/PUUKA Web retrieved at 06:37 (GMT)
Glasgow RCE Info Set up See here for hardware set up: RCESetUp Running the RCE software Make sure to have set up symbolic link to RCE area, i.e. ln s /afs/phas...
RCE Set up: equipment connections Current RCE Set up (lab 345) ATCA 2 slot crate (Asis) 3COM Switch RCEs 8 chips possible to connect per RCE...
Thermal FEA Heat load from RD53A chip For the cooling capacity calculations and the FEA simulations the heat load of the RD53A chip is required. Power from the RD53A...
JoleenPater 2013 08 13 Thermal simulation See this page ThermalFEA Rectangular 3 quad Prototypes To put here: concept sketches assembly photos thermal...
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PCB and wirebonding details for the various Assemblies are given here. Quad Flex v1.11 FLEX1 2.BPX: Quad Flex v1.11 Wire bonding program for BJ820 Zip file...
CO2 cooling The CO2 cooling of the pixel endcap system is being developed by Manchester in collabraotion with Glasgow, Sheffield and Lancaster. Some useful info on...
24th 25th June 2015 Manchester INDICO: https://indico.cern.ch/event/402689/ 10 11th December 2013 Manchester INDICO agenda, slides etc : https://indico.cern.ch/event...
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WP2 meetings WP2 currently holds bi weekly phone/vidyo meetings on Tuesdays at 11:00, face to face meetings every six weeks or so, and occasional `overlap` meetings...
Wafer Probing Info Notes The following modifications should be made to the Probe Card (FE I4A only) Add solder jumper to right side of T1 Add solder jumper...
wafer VPB8WBH Map.pdf: Wafer map VPB8WBH.waprj: waprj file RichardBates 2013 11 27
This wafer is going to LETI for u bump deposition wafermap VMB8WDH.pdf: Wafer Map VMB8WDH.waprj: WAPRJ file RichardBates 2013 02 14
Open Rings Engineering Design page Please add drawings and information as needed to share Comments
Connectivity The UK are developing: Flip chip bump deposition at CEA Leti and flip chip at Advacam Thin chip assemblies with Advacam and CEA Leti...
Flip chip bump deposition at CEA Leti and Flip chip at Advacam The first phase of the development with CEA Leti was the deposition of copper pillars with SAC solder...
Thin chip assemblies To be able to flip chip very thin ROICs addtional work is required to prevent the ROIC from bowing duringthe solder re flow process. At present...
Flip chip bonding at STFC RAL STFC/RAL are developing a fine pitched Indium flip chip process. The samples first have an under bump metal (UBM) layer deposited upon...
The connective task has two main areas of work, TSV and flip chip bonding development. Flip chip bonding at STFC RAL STFC/RAL are developing a fine pitched Indium...
25/07/2012 The Quad assemblies 2 and 3 are made with full thickness ROIC as there is a worry about wafer bow and unbonded edge pixels. Stock Location StatusOfAssemblies...
Indium Bumped Modules This page will serve as a database for characterisation of Indium Bumped Modules developed at RAL. Indium bumps require pressure only to make...
wafer VUB6NCH Map.pdf: Wafer Map RichardBates 2013 11 27 VUB6NCH.waprj: Waprj file
wafer VIB62GH Map.pdf: Wafer Map VIB62GH.waprj: Waprj file RichardBates 2013 11 27
Wafer map wafer V7B8WTH Map.pdf: Wafer Map RichardBates 2013 07 03 V7B8WTH.waprj: Waprj file
This wafer is going to LETI for u bump deposition wafermap V6B8WUH.pdf: Wafer Map V6B8WUH.waprj: Waprj file RichardBates 2013 02 14
SLAC Testbeam May 2014 This page catalogues each experimental setup, GeoIDs and run numbers. For details on reconstruction see here. Enjoy! Quad5, 250x50 DUTs...
`Open Rings` Endcap Layout (Previously known by a number of different names e.g. `concentric diskettes`.) Motivation and Description A couple of talks showing the...
Pixel Endcaps in the LoI (Cartigny) Layout The drawings below show 3 possible types of pixel endcap disks in the LoI, or `Cartigny` layout of the upgraded inner tracker...
JoleenPater 2013 08 13 Stepped Geometry Prototype NB this prototype was shelved in 2013 when the Open Rings layout was adopted. Peter Sutcliffe`s drawings for a...
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Reconstruction This page serves as a central hub for information on the reconstruction and analysis effort of UK Test Beam data. Versions of software in use:...
There are a number of FE I4 wafers A and B that belong to the UK for the ATLAS module upgarde project. Wafers wafer metal.gds.zip: FE I4A Top metal layer GDS...
wafer VJB8WGH Map.pdf: Wafer map RichardBates 2013 11 27
wafer VEB6NSH Map.pdf: Wafer map RichardBates 2013 11 27
wafer VTB8W7H Map.pdf: Wafer map RichardBates 2013 11 27
wafer VYB8XJH Map.pdf: Wafer map RichardBates 2013 11 27
wafer ABPJXGH Map.pdf: ABPJXGH Wafer Map RichardBates 2013 07 12
This wafer was broken during the wafer thinning process wafer VUAYCRH Map.pdf: Wafer map RichardBates 2013 11 26
Meetings Pixel Weekly Face to face meetings FEI 4 testing meeting (Mon @4.30pm CERN) Testbeam Analysis meeting (Tue @4pm CERN)
Under Construction
FEI 4 Documentation Documentation for FEI can be found at https://espace.cern.ch/atlas pixel upgrade elec/Final%20Design/Reference/ (NB: Requires cern id and...
Wafer map wafer VKB8WFH Map.pdf: Wafer Map RichardBates 2013 07 03
ThomasMcMullen 2013 03 08
wafer VWB6IVH Map.pdf: Wafer Map RichardBates 2013 06 13
VTT Assembly10 3200e 100V Tuned.cfg.root: Assembly 10 Configuration File: Threshold 3200e@ ToT8, 100V Det Bias VTT Assembly10 1600e 100V Tuned.cfg.root: Assembly...
VTT Assembly14 3200e 10V Tuned.cfg.root: Assembly 14 Configuation File: Threshold 3200e @ ToT8, 10V Det Bias Assembly14 3200e 10V ToT8 FastTuning.root: Assembly...
Assembly 5 Device IV after flip chip and mouting on the SCC. Assembly5 02082012.pptx: Presentation of scans performed on Assembly 5 VTT Assembly5 3200e 100V...
IV Curves of MPI Sensor MPI IV.xlsx KateDoonan 2012 12 18
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