TWiki> ATLAS/PUUKA Web>Prototyping>ThermalFEA (2015-12-18, RichardBates)

# Thermal FEA

For the cooling capacity calculations and the FEA simulations the heat load of the RD53A chip is required.

Power from the RD53A quad taken as 9.4W

This is the design value, can expect less for the nominal.

### Assumptions

Based on the active area of a quad being 50um x 50um x 400 x 336 x 4

(50 x 50 is the pixel size, 400 x 336 is the number of pixels per chip, 4 for a quad)

Power from the RD53A chip taken as 0.7W/cm2

Power based on 2V with a current of 0.35A/cm2

Current based on 8uA per pixel (results in 0.32A/cm2) and additionally 30mA/cm2 for the power from the periphery.

### What about where to put this heat in the chip?

For the FEA simulations assume we can divide the power between the end of column logic and the pixel area by assuming that the voltage in the active matrix is 1.2V

-> power in active region = 8e-6 x 1.2 x 400 x 336 x 4 =5.16W

And

-> power dissipated in the regulators = 9.4  5.16 W = 4.24 W (used total power  active pixel power defined by 8uA per pixel and 1.2V)

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