Wafer Probing Info Notes The following modifications should be made to the Probe Card (FE I4A only) Add solder jumper to right side of T1 Add solder jumper...
Flip chip bump deposition at CEA Leti and Flip chip at Advacam The first phase of the development with CEA Leti was the deposition of copper pillars with SAC solder...
Thin chip assemblies To be able to flip chip very thin ROICs addtional work is required to prevent the ROIC from bowing duringthe solder re flow process. At present...
Flip chip bonding at STFC RAL STFC/RAL are developing a fine pitched Indium flip chip process. The samples first have an under bump metal (UBM) layer deposited upon...
The connective task has two main areas of work, TSV and flip chip bonding development. Flip chip bonding at STFC RAL STFC/RAL are developing a fine pitched Indium...
25/07/2012 The Quad assemblies 2 and 3 are made with full thickness ROIC as there is a worry about wafer bow and unbonded edge pixels. Stock Location StatusOfAssemblies...
Indium Bumped Modules This page will serve as a database for characterisation of Indium Bumped Modules developed at RAL. Indium bumps require pressure only to make...
SLAC Testbeam May 2014 This page catalogues each experimental setup, GeoIDs and run numbers. For details on reconstruction see here. Enjoy! Quad5, 250x50 DUTs...
`Open Rings` Endcap Layout (Previously known by a number of different names e.g. `concentric diskettes`.) Motivation and Description A couple of talks showing the...
Pixel Endcaps in the LoI (Cartigny) Layout The drawings below show 3 possible types of pixel endcap disks in the LoI, or `Cartigny` layout of the upgraded inner tracker...
JoleenPater 2013 08 13 Stepped Geometry Prototype NB this prototype was shelved in 2013 when the Open Rings layout was adopted. Peter Sutcliffe`s drawings for a...
Reconstruction This page serves as a central hub for information on the reconstruction and analysis effort of UK Test Beam data. Versions of software in use:...
There are a number of FE I4 wafers A and B that belong to the UK for the ATLAS module upgarde project. Wafers wafer metal.gds.zip: FE I4A Top metal layer GDS...
FEI 4 Documentation Documentation for FEI can be found at https://espace.cern.ch/atlas pixel upgrade elec/Final%20Design/Reference/ (NB: Requires cern id and...
Assembly 5 Device IV after flip chip and mouting on the SCC. Assembly5 02082012.pptx: Presentation of scans performed on Assembly 5 VTT Assembly5 3200e 100V...
IV Characteristics of the FBK 7 assembly: IV Curve FBK 200212.xlsx Details of noise characterisation of the FBK 7 assembly: FBK Noise.pptx Further information on FBK...
Unfortunately this assembly was broken due to an accident with the probe station. The detector of the assembly was being IVed on arrival in Glasgow, before wirebonding...
This is a green chi. Sent to RAL. Prim List used to tune the chip $ Assembly14 Fast Tuning 3200e.prl.root: Data file from Prim List $ 2012 10 08 Wafer...
RichardBates 2011 04 16 See attachments for cool box drawing for EUDET telescope as of Sept2012, note this is not compatible with the QUAD module due as it is not...
JoleenPater 2012 02 16 SimonBrown 2012 02 23 This page contains information about the Data Multiplexer for the Pixel Modules. The Data Multiplexer is intended...