Some Red chips sent to RAL and MPI

• Die_Status-3-2.xlsx: Die status as of 27/7/2012

14/7/2012

2 Green chips sent to glasgow for wafer probing

• Die_Status-3.xlsx: Die status as of 14/6/2012

28/5/2012

4 more single chips and first quad assemblied.

Die status is now:

• Die_Status-2.xlsx: Die status as of 28/5/2012

After the first Flip-Chip of 6 single assmeblies we have 32 die reminaing. 6 were damaged during the flip-chip process and will be investigated.

• Die_Status.xlsx: Die Status

The remiaing die on this wafer as of 20th April

• Chips_remaining_18-April-2012.ppt: Chips remaining as of 18th April 2012

From these 46 was glued to a Single Chip Card and tested in Glagsow. However, there was a problem with too much electrically conductive glue causing an electrical short between VDDA2 and GND. Therefore this chip could not be tested.

The likelyhood of demagaed due to the bump deposition and wafer thinning is small. Quated at 4% on numbers collected 4-5 years ago by VTT. So becided to go ahead with flip-chip assembly any how.

After thinnning this wafer suffered damage. The laser scribed ID mark was stuck to the blue tape and could not be released. Upon removal of the wafer from the tape the wafer cracked.

• ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf: ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf

Die that were damaged and returned to Glasgow are: 29, 30 and 39.

Red Die returned to Glasgow for setting up the probe card: 1, 13, 14 and 35

Yellow Die returned to Glasgow for testing the probe card: 36, 43

Green Die returned to Glasgow to confirm that the deposition of the bumps does not affect the ASIC characteristics: 46

The wafer map

• V6ABC1H.ppt: Picture of the wafer map

The Wafer test results

• WafertestingResults_V6ABC1H.xlsx: Probe results

Pictures of bumps on the wafer from VTT

• 10x -1.jpg: a photo from the chip corner:
  

• Bumps x20.jpg: a photo using 20 x magnification:
  

• Cu and solder x50.jpg: Cu residues after the field metal (Cu) etching.:
  

VTT spotted quite a few of these on the wafer, but they do not seem to be a threat for the bumping yield as they do not form short circuits between the bumps – they look ugly but do no harm. The reason behind the residues can be: a) 50 µm pitch, b) topography around the bump pad or c) something else. As a consequence, we have to prolong the etching time with some seconds.

• Dummy bumps x5.jpg: This photo is from the wafer perimeter, where the ROCs are not complete.:
  

VTT comment: I just wanted to take a photo from a ROC with a clear id marked with solder bumps.

-- RichardBates - 2012-02-22