Some Red chips sent to RAL and MPI


2 Green chips sent to glasgow for wafer probing


4 more single chips and first quad assemblied.

Die status is now:

After the first Flip-Chip of 6 single assmeblies we have 32 die reminaing. 6 were damaged during the flip-chip process and will be investigated.

The remiaing die on this wafer as of 20th April

From these 46 was glued to a Single Chip Card and tested in Glagsow. However, there was a problem with too much electrically conductive glue causing an electrical short between VDDA2 and GND. Therefore this chip could not be tested.

The likelyhood of demagaed due to the bump deposition and wafer thinning is small. Quated at 4% on numbers collected 4-5 years ago by VTT. So becided to go ahead with flip-chip assembly any how.

After thinnning this wafer suffered damage. The laser scribed ID mark was stuck to the blue tape and could not be released. Upon removal of the wafer from the tape the wafer cracked.

Die that were damaged and returned to Glasgow are: 29, 30 and 39.

Red Die returned to Glasgow for setting up the probe card: 1, 13, 14 and 35

Yellow Die returned to Glasgow for testing the probe card: 36, 43

Green Die returned to Glasgow to confirm that the deposition of the bumps does not affect the ASIC characteristics: 46

The wafer map

The Wafer test results

Pictures of bumps on the wafer from VTT

  • 10x -1.jpg: a photo from the chip corner:

  • Bumps x20.jpg: a photo using 20 x magnification:

  • Cu and solder x50.jpg: Cu residues after the field metal (Cu) etching.:

VTT spotted quite a few of these on the wafer, but they do not seem to be a threat for the bumping yield as they do not form short circuits between the bumps – they look ugly but do no harm. The reason behind the residues can be: a) 50 Ám pitch, b) topography around the bump pad or c) something else. As a consequence, we have to prolong the etching time with some seconds.

  • Dummy bumps x5.jpg: This photo is from the wafer perimeter, where the ROCs are not complete.:

VTT comment: I just wanted to take a photo from a ROC with a clear id marked with solder bumps.

-- RichardBates - 2012-02-22

Topic attachments
I AttachmentSorted ascending History Action Size Date Who Comment
JPEGjpg 10x_-1.jpg r1 manage 70.1 K 2012-02-22 - 11:14 RichardBates 10x -1.jpg: a photo from the chip corner
JPEGjpg Bumps_x20.jpg r1 manage 56.7 K 2012-02-22 - 11:15 RichardBates Bumps x20.jpg: a photo using 20 x magnification
PowerPointppt Chips_remaining_18-April-2012.ppt r1 manage 780.5 K 2012-04-20 - 12:56 RichardBates Chips remaining as of 18th April 2012
JPEGjpg Cu_and_solder_x50.jpg r1 manage 33.0 K 2012-02-22 - 11:15 RichardBates Cu and solder x50.jpg: Cu residues after the field metal (Cu) etching.
Microsoft Excel Spreadsheetxlsx Die_Status-2.xlsx r1 manage 34.3 K 2012-06-06 - 15:25 RichardBates Die status as of 28/5/2012
Microsoft Excel Spreadsheetxlsx Die_Status-3-2.xlsx r2 r1 manage 34.8 K 2012-07-27 - 13:41 RichardBates Die status as of 27/7/2012
Microsoft Excel Spreadsheetxlsx Die_Status-3.xlsx r1 manage 34.3 K 2012-06-14 - 14:39 RichardBates Die status as of 14/6/2012
Microsoft Excel Spreadsheetxlsx Die_Status.xlsx r1 manage 34.2 K 2012-04-20 - 14:24 RichardBates Die Status
JPEGjpg Dummy_bumps_x5.jpg r1 manage 81.2 K 2012-02-22 - 11:16 RichardBates Dummy bumps x5.jpg: This photo is from the wafer perimeter, where the ROCs are not complete.
PDFpdf ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf r1 manage 490.1 K 2012-04-16 - 14:06 RichardBates  
PowerPointppt V6ABC1H.ppt r1 manage 557.0 K 2012-02-22 - 11:11 RichardBates Picture of the wafer map
Microsoft Excel Spreadsheetxlsx WafertestingResults_V6ABC1H.xlsx r1 manage 22.5 K 2012-02-22 - 11:11 RichardBates Probe results
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Topic revision: r7 - 2012-07-27 - RichardBates
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