Thin film hybrid in MCM-D technology

Processing on blank silicon wafers to determine the feasibility of building a fully functional circuit in this technology. The cricuit has five metal layers and hosts 20 front-end ASICS. Electrically it is an exact copy of the silicon tracker upgrade hybrid designed in Liverpool.

Specification of first version

Photos at reception of first thin film hybrid batch

Post processing of sensor wafer: Run 1

Processing on electrical and mechanical grade sensor wafers to investigate the influence on the sensor performance. The processing involved a single metal layer, with the cross-section shown in the figure below.

Wafer and sensor numbering scheme Run 1

The wafers are marked with sensor number at the wafer edge close to the larger straight section of the border. The individual sensors are labelled by their X and Y positions on the wafer. The classification of the wafers and the definition of the wafer number can be found in SensorNumbering.pdf.

Electrical measurements of Run 1

I/V and C/V measurements of all sensors before dicing

I/V measurements of all sensors after dicing

Inter-strip capacitance measurements of all sensors before dicing

Capacitance between strip and GND plane

Summary of capacitive load measurements

Inter-strip resistiance

Punch-through measurement

Documentation and photos

Photos at reception of the wafers

Bias bonds on measured wafers

Yield measurements

Reference documents and presentations

Mechanical measurements

Sensor flatness

Mechanical measurements for Wafers 4 and 17

Sensors w04

Sensors w17

-- LarsEklund - 21 Nov 2008