• V6ABC1H.ppt: Picture of the wafer map

The Wafer test results

• WafertestingResults_V6ABC1H.xlsx: Probe results

Pictures of bumps on the wafer from VTT

• 10x -1.jpg: a photo from the chip corner:
  

• Bumps x20.jpg: a photo using 20 x magnification:
  

• Cu and solder x50.jpg: Cu residues after the field metal (Cu) etching.:
  

VTT spotted quite a few of these on the wafer, but they do not seem to be a threat for the bumping yield as they do not form short circuits between the bumps – they look ugly but do no harm. The reason behind the residues can be: a) 50 µm pitch, b) topography around the bump pad or c) something else. As a consequence, we have to prolong the etching time with some seconds.

• Dummy bumps x5.jpg: This photo is from the wafer perimeter, where the ROCs are not complete.:
  

VTT comment: I just wanted to take a photo from a ROC with a clear id marked with solder bumps.

-- RichardBates - 2012-02-22