(r3) V6ABC1H < ATLAS/PUUKA

ATLAS/PUUKA Web>Tasks>Modules>Our_FEI4_wafers>V6ABC1H (revision 3) (raw view)~~EditAttach~~

The remiaing die on this wafer as of 20th April

   * [[%ATTACHURL%/Chips_remaining_18-April-2012.ppt][Chips_remaining_18-April-2012.ppt]]: Chips remaining as of 18th April 2012

From these 46 was glued to a Single Chip Card and tested in Glagsow. However, there was a problem with too much electrically conductive glue causing an electrical short between VDDA2 and GND. Therefore this chip could not be tested.

The likelyhood of demagaed due to the bump deposition and wafer thinning is small. Quated at 4% on numbers collected 4-5 years ago by VTT. So becided to go ahead with flip-chip assembly any how.

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After thinnning this wafer suffered damage. The laser scribed ID mark was stuck to the blue tape and could not be released. Upon removal of the wafer from the tape the wafer cracked.

   * [[%ATTACHURL%/ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf][ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf]]: ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf

Die that were damaged and returned to Glasgow are: 29, 30 and 39.

Red Die returned to Glasgow for setting up the probe card: 1, 13, 14 and 35

Yellow Die returned to Glasgow for testing the probe card: 36, 43

Green Die returned to Glasgow to confirm that the deposition of the bumps does not affect the ASIC characteristics: 46

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The wafer map

   * [[%ATTACHURL%/V6ABC1H.ppt][V6ABC1H.ppt]]: Picture of the wafer map

The Wafer test results
   * [[%ATTACHURL%/WafertestingResults_V6ABC1H.xlsx][WafertestingResults_V6ABC1H.xlsx]]: Probe results

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Pictures of bumps on the wafer from VTT
   * 10x -1.jpg: a photo from the chip corner: <br /> <img width="640" alt="10x_-1.jpg" src="%ATTACHURLPATH%/10x_-1.jpg" height="480" />

   * Bumps x20.jpg: a photo using 20 x magnification: <br /> <img width="640" alt="Bumps_x20.jpg" src="%ATTACHURLPATH%/Bumps_x20.jpg" height="480" />

   * Cu and solder x50.jpg: Cu residues after the field metal (Cu) etching.: <br /> <img width="640" alt="Cu_and_solder_x50.jpg" src="%ATTACHURLPATH%/Cu_and_solder_x50.jpg" height="480" />

VTT spotted quite a few of these on the wafer, but they do not seem to be a threat for the bumping yield as they do not form short circuits between the bumps &ndash; they look ugly but do no harm. The reason behind the residues can be: a) 50 µm pitch, b) topography around the bump pad or c) something else. As a consequence, we have to prolong the etching time with some seconds.

   * Dummy bumps x5.jpg: This photo is from the wafer perimeter, where the ROCs are not complete.: <br /> <img width="640" alt="Dummy_bumps_x5.jpg" src="%ATTACHURLPATH%/Dummy_bumps_x5.jpg" height="480" />

VTT comment: I just wanted to take a photo from a ROC with a clear id marked with solder bumps.

-- Main.RichardBates - 2012-02-22

Attachments

Topic attachments
I	Attachment	History	Action	Size	Date	Who	Comment
jpg	10x_-1.jpg	r1	manage	70.1 K	2012-02-22 - 11:14	RichardBates	10x -1.jpg: a photo from the chip corner
jpg	Bumps_x20.jpg	r1	manage	56.7 K	2012-02-22 - 11:15	RichardBates	Bumps x20.jpg: a photo using 20 x magnification
ppt	Chips_remaining_18-April-2012.ppt	r1	manage	780.5 K	2012-04-20 - 12:56	RichardBates	Chips remaining as of 18th April 2012
jpg	Cu_and_solder_x50.jpg	r1	manage	33.0 K	2012-02-22 - 11:15	RichardBates	Cu and solder x50.jpg: Cu residues after the field metal (Cu) etching.
jpg	Dummy_bumps_x5.jpg	r1	manage	81.2 K	2012-02-22 - 11:16	RichardBates	Dummy bumps x5.jpg: This photo is from the wafer perimeter, where the ROCs are not complete.
pdf	ROW-V6ABC1H-cracked-JS-16-Mar-2012.pdf	r1	manage	490.1 K	2012-04-16 - 14:06	RichardBates
ppt	V6ABC1H.ppt	r1	manage	557.0 K	2012-02-22 - 11:11	RichardBates	Picture of the wafer map
xlsx	WafertestingResults_V6ABC1H.xlsx	r1	manage	22.5 K	2012-02-22 - 11:11	RichardBates	Probe results

Topic revision: r3 - 2012-04-20 - RichardBates

ATLAS/PUUKA