(r3) WaferTesting < DetDev

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Descriprtion of the water testing of ASICS at Glasgow

---++ Introduction

The following is a decripton of the setup used to test wafers of ABCn ASICS at Glasgow.

The setup uses a Cascade semi automaitc propbe station, with a cutosm built probe card. The probe card is connected to a PCB driver card, which sends signals and data to and from the PC. 2 NI cards are used for signalling, voltage sourced for power, multimeters for measuring the DACs and an adapted verstion of SCTDAQ is used for control software

---++ Hardware
<table align="center" border="0"> <tbody> <tr> <td>TTi TSX3510P</td> <td>TTi CPX 2000</td> <td>Agilent 34401A</td> <td>Agilent 34401A</td> </tr> <tr> <td><img alt="" src="http://img811.imageshack.us/img811/3444/tsx1820.jpg" /></td> <td><img alt="" src="http://img232.imageshack.us/img232/7171/cpx400dpf280.jpg" /></td> <td><img width="282" alt="" src="http://img15.imageshack.us/img15/7791/34401aimage.jpg" height="172" /></td> <td><img width="337" alt="" src="http://img15.imageshack.us/img15/7791/34401aimage.jpg" height="158" /></td> </tr> <tr> <td>2.5V for ABCn</td> <td>

5.5V for Driver board

Voltage for 80MHz clock source
</td> <td>Meter for ABCn multiplexer ouput</td> <td>Meter for monitoring output of the ABCn analogue regulator</td> </tr> </tbody> </table>
---+++ Driver Card
---+++ <img alt="" src="http://img100.imageshack.us/img100/4201/clipboard01popopo.gif" /> <img width="317" alt="" src="http://img824.imageshack.us/img824/2125/img0730mm.jpg" height="393" />

---++++++ Connections
   * 2 64 pin twist & flat cables 
      * Connects the Driver card to the probe card
      * Supplies the LVDS, CMOS signals, control lines etc
   * DB9 -&gt; 4 Banana leads 
      * 2.5V provides ABCn power
      * ~4.5V for driver board (locally regulated). Taken to 3.3V, 2.5V & 2.0V by local regulators
   * Lemo 2 pin 
      * Analogue output
      * Multiplexer out from ABCn to multimeter
      * Bandgap reference for Vreg on ABCn
   * 2 Large multi pin connectors 
      * connected to NI cards in PC
   * PL7 
      * Analogue regulator output
      * To 2nd multimeter
---+++ Probe Card

<img width="438" alt="" src="http://img821.imageshack.us/img821/4955/img1016v.jpg" height="583" /> <img width="335" alt="" src="http://img821.imageshack.us/img821/2111/clipboard01gggggg.gif" height="342" />
---+++ Probe Station

<img width="406" alt="Probe Station" src="http://img546.imageshack.us/img546/2120/img1017w.jpg" title="Probe Station" height="541" />
---+++ NI Cards
---+++ Source & Multitmeters

---++ Software

<img width="423" alt="" src="https://twiki.cern.ch/twiki/pub/Atlas/SCTUpDAQDown/waferGuiInAction.png" height="426" /> <img width="455" alt="" src="http://img854.imageshack.us/img854/6157/clipboard0111.png" height="425" />

   * Root 5,26
   * Visual Studio Express 2008
   * Labview 8.6
   * SCTDAQ

Test Sequence

   * Digital Test Vectors 
      * Check all registres can be written and sent back
      * Test token receive and send data
      * Same for other side of chip
      * Master mode with 80MHz clock
      * Stops at failure and flasgs as Bad (Red)
   * Analogue DACs via the multiplexer output
   * Analogue front end test 
      * 2 point gain (1.5, 2 & 2.5 fC trim DACS @ 0)
      * Threshold scan at full range of trim DACS (2fC, trimDAC :@ max)
---++ Instructions
   * In root, .x Wafter.cpp
   * Loads STGUI.cpp
   1 Test Bonded ASIC Test Die 
      * Test Single chip (manual and move)

2. Test single ASIC
   * 
      * Place single asic on chuck
      * Turn vacumn on
      * Align chip 
         * Roate in Abhle
         * align in x and y
      * Find point of first contact 
         * 2.5V source will draw xcurrent (~0.14A)
      * Over travel can be appklied up to 60 microns over first contact
      * Check for probe marks on each pad

3. Test wafer
   * 
      * Place Wafer on chuck and vacum 
         * align at this stage as best as possible x + y
      * Align wafer (max L + R points)
      * Align top left asic for x+y
      * Check if still in alignment for bottom right wafer
      * Test wafer option on software
---++++++ Notes

Cuts for failures as follows:
   * Digital (Red)
   * Power (Blue)
   * Analog (Yellow)

If 3 Digital fails in a row, wafer testing will fail
Topic revision: r3 - 2011-11-01 - AndrewBlue
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