Introduction

The following is a description of the setup used to test wafers of ABCn ASICS at Glasgow.

The setup uses a Cascade semi automatic probe station, with a custom built probe card. The probe card is connected to a PCB driver card, which sends signals and data to and from the PC. 2 NI cards are used for signalling, voltage sourced for power, multimeters for measuring the DACs and an adapted verstion of SCTDAQ is used for control software

Hardware

TTi TSX	TTi CPX 2000	Agilent 34401A	Agilent 34401A
2.5V for ABCn	5.5V for Driver board Voltage for 80MHz clock source	Meter for ABCn multiplexer ouput	Meter for monitoring output of the ABCn analogue regulator

Driver Card

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Connections

• 2 64 pin twist & flat cables
  • Connects the Driver card to the probe card
  • Supplies the LVDS, CMOS signals, control lines etc
• DB9 -> 4 Banana leads
  • 2.5V provides ABCn power
  • ~4.5V for driver board (locally regulated). Taken to 3.3V, 2.5V & 2.0V by local regulators
• Lemo 2 pin
  • Analogue output
  • Multiplexer out from ABCn to multimeter
  • Bandgap reference for Vreg on ABCn
• 2 Large multi pin connectors
  • connected to NI cards in PC
• PL7
  • Analogue regulator output
  • To 2nd multimeter

Probe Card

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The custom cantilever epoxy probe card, made by Rucker and Kolls, Milpitas, CA, has 122 probes.

In place of the usual edge connector, 0.1” header pins are used to provide connectivity, a deliberate choice to give added clearance
above the wafer surface during probing.

The card has also been shortened to minimize the trace lengths and all LVDS pairs are terminated with 100 ohm resistors at the probe ring.

Probe Station

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• Cascade Microtech model S300 probe station
• The machine, which has a 12” chuck, can accommodate the 8” ABCN-25 wafers.

NI Cards

Commercial off the shelf (COTS) hardware from National
struments (NI) is used to read out each ASIC

Fast test vectors are generated by the NI PCI-6562 400 Mb/s Digital Waveform Generator/Analyzer, which has 16 LVDS

Software

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• Root 5,26
• Visual Studio Express 2008
• Labview 8.6
• SCTDAQ

Test Sequence

Digital Test Vectors

Four test vector blocks are used to test the complete digital functionality of the chip

Bearing in mind that ABCN-25 has built-in shun regulator functionality to be used as part of a serially powered
system, each test is performed under different powering conditions such that the basic functionality of each of theshunt blocks may be demonstrated.

For a chip to be considered good, it must return no errors for any vector block.

In addition, for tests executed with serial powering shunts active, the full source current must be drawn at the expected
voltage.

DAC Characterisation

The ABCN-25 design includes an on-chip multiplexer which enables each of a number of internal analogue signals to be routed to an external voltmeter.

These nodes include the output of each of the chip’s Digital to Analogue Converters (DACs).

During the wafer probing, a digital voltmeter is used to record 8 points to characterise each DAC, and a single measurement for each static node available through the
multiplexer.

Additional measurements are made of the bandgap reference made available at the vbgtest pin and of the analogue voltage derived from the digital supply by the chip’s
built in regulator.

Chips having DACs with anomalous single point measurements or DAC step sizes are considered as rejects.

Analogue Characterisation

Each ABCN-25 readout channel has a 5-bit threshold DAC, used to compensate for offset variations across the chip.

In addition the step size of these DACs , known as the trim range, may be set to one of 8 possible levels.

All wafer probing data is recorded using trim range 4.

With all trim DACs set to zero, threshold scans are made for charges of 1.5fC, 2.0fC and 2.5fC, injected using the ABCN-25’s
internal calibration circuitry.

A fourth threshold scan is then made for an injected charge of 2.0fC, but this time the trim DACs are set to 31.

This data may be analysed to calculate the gain, offset and noise of each channel and to estimate the number of channels which may be trimmed using the selected
trim range.

For a chip to be considered as good, it must have no more than one bad (dead, stuck or untrimmable) channel.

Instructions

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• In root, .x Wafter.cpp
• Loads STGUI.cpp

1. Test Bonded ASIC Test Die
   • Test Single chip (manual and move)

2. Test single ASIC

• • Place single asic on chuck
  • Turn vacumn on
  • Align chip
    • Roate in Abhle
    • align in x and y
  • Find point of first contact
    • 2.5V source will draw xcurrent (~0.14A)
  • Over travel can be appklied up to 60 microns over first contact
  • Check for probe marks on each pad

3. Test wafer

• • Place Wafer on chuck and vacum
    • align at this stage as best as possible x + y
  • Align wafer (max L + R points)
  • Align top left asic for x+y
  • Check if still in alignment for bottom right wafer
  • Test wafer option on software

Notes

Cuts for failures as follows:

• Digital (Red)
• Power (Blue)
• Analog (Yellow)

If 3 Digital fails in a row, wafer testing will fail

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Strobe Delay

1. Go to a known working location, run an ASIC test.

2.  lift the probes again, power on the Tti manually, execute configs (action menu).

3.  from the action menu, run an ABCNburst to verify contact and that the hardware is all set up for threshold scans (should be left that way at end of ASIC test)

4.  from the test menu, run a strobe delay scan.