Introduction

The following is a decripton of the setup used to test wafers of ABCn ASICS at Glasgow.

The setup uses a Cascade semi automaitc propbe station, with a cutosm built probe card. The probe card is connected to a PCB driver card, which sends signals and data to and from the PC. 2 NI cards are used for signalling, voltage sourced for power, multimeters for measuring the DACs and an adapted verstion of SCTDAQ is used for control software

Hardware

TTi TSX3510P	TTi CPX 2000	Agilent 34401A	Agilent 34401A
2.5V for ABCn	5.5V for Driver board Voltage for 80MHz clock source	Meter for ABCn multiplexer ouput	Meter for monitoring output of the ABCn analogue regulator

Driver Card

Connections

• 2 64 pin twist & flat cables
  • Connects the Driver card to the probe card
  • Supplies the LVDS, CMOS signals, control lines etc
• DB9 -> 4 Banana leads
  • 2.5V provides ABCn power
  • ~4.5V for driver board (locally regulated). Taken to 3.3V, 2.5V & 2.0V by local regulators
• Lemo 2 pin
  • Analogue output
  • Multiplexer out from ABCn to multimeter
  • Bandgap reference for Vreg on ABCn
• 2 Large multi pin connectors
  • connected to NI cards in PC
• PL7
  • Analogue regulator output
  • To 2nd multimeter

Probe Card

Probe Station

NI Cards

Source & Multitmeters

Software

• Root 5,26
• Visual Studio Express 2008
• Labview 8.6
• SCTDAQ

Test Sequence

• Digital Test Vectors
  • Check all registres can be written and sent back
  • Test token receive and send data
  • Same for other side of chip
  • Master mode with 80MHz clock
  • Stops at failure and flasgs as Bad (Red)
• Analogue DACs via the multiplexer output
• Analogue front end test
  • 2 point gain (1.5, 2 & 2.5 fC trim DACS @ 0)
  • Threshold scan at full range of trim DACS (2fC, trimDAC :@ max)

Instructions

• In root, .x Wafter.cpp
• Loads STGUI.cpp

1. Test Bonded ASIC Test Die
   • Test Single chip (manual and move)

2. Test single ASIC

• • Place single asic on chuck
  • Turn vacumn on
  • Align chip
    • Roate in Abhle
    • align in x and y
  • Find point of first contact
    • 2.5V source will draw xcurrent (~0.14A)
  • Over travel can be appklied up to 60 microns over first contact
  • Check for probe marks on each pad

3. Test wafer

• • Place Wafer on chuck and vacum
    • align at this stage as best as possible x + y
  • Align wafer (max L + R points)
  • Align top left asic for x+y
  • Check if still in alignment for bottom right wafer
  • Test wafer option on software

Notes

Cuts for failures as follows:

• Digital (Red)
• Power (Blue)
• Analog (Yellow)

If 3 Digital fails in a row, wafer testing will fail