Difference: MCMD (17 vs. 18)

The photos were taken at reception of the wafers, but after wafers w09 and w14 had some of their ground planes bonded to the bias rails. Bond tests and tuning were done on the large metallised area at the bottom of w09. The bonds are visible in the photos. The bias bond locations are described in BiasBonds.pdf.

Full wafer views

Close-up views on a few sensors on w14

Meshed GND plane, full view

Bias bond, close-up

Meshed GND plane, top half

Meshed GND plane, full view

Solid GND plane, top half

Triangular GND plane, full view

Close-up views on a few features on w14

Ground planes: solid, meshed, meshed (bond pad)

Bias and guard ring connections: bias and guard rings, bias ring via, bias bond (triangular), bias bond (meshed)

Strip connections: overview, zoom 1, zoom 2, zoom 3, bond pad, double vias

Bias resistor connections: resistor via, zoom

A set of lines with decreasing line width and spacing were put on the mask to assess the resolution of the process. Starting with 10 lines of 5 um line width and spacing, increasing with 5 um for each set of lines. As seen in the overview picture all lines down to 10 um line width and spacing were correctly reproduced. However, the smallest pitch region became merged into one solid metallisation as can be seen in the close-up.

IV and CV measurments

Measurements performed by Alex Chilingarov, University of Lancaster and analysis is done by Lars Eklund, University of Glasgow.

Summary plots of I/V and C/V performance for wafer 09 (12 µm BCB)

The scale of the I/V graph covers the range of 25 of the 26 sensors on wafer 09. Sensor X5Y3 breakes down at low voltages, see separate I/V. Sensors X5Y1, X5Y2 and X5Y4 were ramped to 600 V with leakage current of 40, 33 and 31 nA at 600V. Sensor X5Y1 was kept at 600 V for 30 min and is the only sensor that shows a clear change in reverse current over time, but with signs of saturation. See stability graph.

Depletion voltage extracted from C/V

The depletion voltage was extracted by fitting two first order polynomials to the 1/C2 vs. Vbias graph. The first straight line is fitted between 0 and 30 V and the second straight line is fitted between 150 and 400 V. The depletion voltage is defined as the intersection between these two lines. The depletion voltage is displayed both as a histogram and as a map where the depletion voltage is displayed in its position on the wafer, with coordinates as defined in the figure above. The depletion voltage could not be determined for X5Y3 due to its breakdown, hence the histograms include 25 sensors.

Summary plots of I/V and C/V performance for wafer 14 (6 µm BCB)

Until present 19 sensors have been teste of which 18 are inclueded in the plots. Sensor X0Y4 broke down a very low voltage and is excluded from the analysis presented here.

Depletion voltage extracted from C/V

The depletion voltage was extracted by fitting two first order polynomials to the 1/C2 vs. Vbias graph. The first straight line is fitted between 0 and 30 V and the second straight line is fitted between 150 and 400 V. The depletion voltage is defined as the intersection between these two lines. The depletion voltage is displayed both as a histogram and as a map where the depletion voltage is displayed in its position on the wafer, with coordinates as defined in the figure above. Sensor X0Y4 is not inclued in the depletion voltage plots since it broke down at low voltages.

I/V ramp to 1000 V for two sensors on w14

Sensor X5Y1 was kept at 1000V and a break down started to develop at which point it was ramped down immediately

Plots combining the I/V and C/V data for wafer 09 and 14

The following plot show the reverse current at 400 V bias for all measured sensors on wafer 09 and 14.

The following plot shows the reverse current at 400 and 600 V for w 14 for all measured sensors