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---++ Photos at reception of Run 1 wafers The photos were taken at reception of the wafers, but after wafers w09 and w14 had some of their ground planes bonded to the bias rails. Bond tests and tuning were done on the large metallised area at the bottom of w09. The bonds are visible in the photos. The bias bond locations are described in [[%ATTACHURL%/BiasBonds.pdf][BiasBonds.pdf.]] *Full wafer views* | | 6 um BCB | 12 um BCB | | Electrical | [[%ATTACHURL%/w14_6umBCBElectrical_atReception.JPG][w14]], [[%ATTACHURL%/w15_6umBCBElectrical_atReception.JPG][w15]] | [[%ATTACHURL%/w08_12umBCBElectrical_atReception.JPG][w08]], [[%ATTACHURL%/w09_12umBCBElectrical_atReception.JPG][w09]] | | Mechanical | [[%ATTACHURL%/w17_6umBCBMechanical_atReception.JPG][w17]], [[%ATTACHURL%/w18_6umBCBMechanical_atReception.JPG][w18]], [[%ATTACHURL%/w19_6umBCBMechanical_atReception.JPG][w19]] | [[%ATTACHURL%/w04_12umBCBMechanical_atReception.JPG][w04]], [[%ATTACHURL%/w05_12umBCBMechanical_atReception.JPG][w05]], [[%ATTACHURL%/w16_12umBCBMechanical_atReception.JPG][w16]] | *Close-up views on a few sensors on w14* [[%ATTACHURL%/meshGNDPlane_w14_X3Y2.JPG][Meshed GND plane, full view]] [[%ATTACHURL%/meshGNDPlane_w14_X0Y1.JPG][Bias bond, close-up]] [[%ATTACHURL%/meshGNDPlane_w14_X4Y1.JPG][Meshed GND plane, top half]] [[%ATTACHURL%/meshGNDPlane_w14_X4Y2.JPG][Meshed GND plane, full view]] [[%ATTACHURL%/solidGNDPlane_w14_X3Y1.JPG][Solid GND plane, top half]] [[%ATTACHURL%/triGNDPlane_w14_X3Y0.JPG][Triangular GND plane, full view]] *Close-up views on a few features on w14* Ground planes: [[%ATTACHURL%/solidGNDPlane.jpg][solid]], [[%ATTACHURL%/meshedGNDPlane.jpg][meshed]], [[%ATTACHURL%/meshedGNDPlane_withBondPad2.jpg][meshed (bond pad)]] Bias and guard ring connections: [[%ATTACHURL%/biasGuardRings.jpg][bias and guard rings]], [[%ATTACHURL%/biasRingVia_zoom.JPG][bias ring via]], [[%ATTACHURL%/biasBonds_tri.jpg][bias bond (triangular)]], [[%ATTACHURL%/meshedGNDPlane_withBondPad.jpg][bias bond (meshed)]] Strip connections: [[%ATTACHURL%/stripPadConnections.jpg][overview]], [[%ATTACHURL%/stripPadConnections_zoom1.jpg][zoom 1]], [[%ATTACHURL%/stripPadConnections_zoom2.jpg][zoom 2]], [[%ATTACHURL%/stripPadConnections_zoom3.jpg][zoom 3]], [[%ATTACHURL%/bondPad.jpg][bond pad]], [[%ATTACHURL%/doubleVias.jpg][double vias]] Bias resistor connections: [[%ATTACHURL%/biasResVias.jpg][resistor via]], [[%ATTACHURL%/biasResVia_zoom.jpg][zoom]] A set of lines with decreasing line width and spacing were put on the mask to assess the resolution of the process. Starting with 10 lines of 5 um line width and spacing, increasing with 5 um for each set of lines. As seen in the [[%ATTACHURL%/lineResolution.jpg][overview picture]] all lines down to 10 um line width and spacing were correctly reproduced. However, the smallest pitch region became merged into one solid metallisation as can be seen in the [[%ATTACHURL%/lineResolution_zoom.jpg][close-up]]. -- Main.LarsEklund - 16 Dec 2008
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Topic revision: r6 - 2009-02-06
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RichardBates
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