IndiumFlpChipWithRAL < ATLAS/PUUKA

ATLAS/PUUKA Web>Tasks>Connectivity_>IndiumFlpChipWithRAL (2014-10-20, RichardBates) (raw view)
---+ Flip-chip bonding at STFC-RAL

STFC/RAL are developing a fine pitched Indium flip-chip process. The samples first have an under bump metal (UBM) layer deposited upon them where the bump is to be grown. The UBM used to date is Ti/W, Ni, Au. The Ti/W is an adhesion layer to the Aluminium pad of the device. The nickel is the solderable metal layer and the Au is an oxidation barrier. The indium is deposited in a thermal reactor at RAL. The Indium is heated under vacuum and condenses on the sample that is held at a lower temperature. The samples can then be flip-chipped bonded. The flip-chip process is to work at room temperature or slightly elevated temperatures.

There is some worry that the Indium bumps require more pressure to form a bump than should be the case. One suggestion for this high pressure is that the gold used in the UBM is moving into the Indium and forming an Indium/Gold alloy which requires more force to deform. A SEM/FIB/EDX study of an Indium bump formed on a silicon substrate was performed in Glasgow to try and test the hypothesis that the gold had moved into the Indium. The report is found here:

   * [[%PUBURL%/ATLAS/PUUKA/Connectivity/Report_on_SEM_Secondary_electron_images_and_EDX_measurements_on_In_bumps_from_RAL.docx][Report_on_SEM_Secondary_electron_images_and_EDX_measurements_on_In_bumps_from_RAL.docx]]: Report on SEM for Indium bump from RAL
The report's conclusion is that the gold does indeed appear to have migrated into the Indium bump.

---++ First Indium Flip-chip bonded FE-I4

The first indium assembly wafer ID : VMB6NJH die 3

Sensor : CPII Live FE-I4 MPI Guard IBL

<br /> [[%PUBURLPATH%/ATLAS/PUUKA/Connectivity/Indium_BumpYield_28032014.pptx][Indium_BumpYield_28032014.pptx]]: Bump Yield Studies March 2013

---++ Indium Flip-Chipped Modules September 2014
---+ 

Indium bumps require pressure only to make connections so no high temperatures are required to melt alloy, which reduces bowing effects.

---++++ Modules under test:

| *ID* | *Bond Force* | *Comment* |
| 14-07-24-S2 | 20kg | biased to 40V |
| 14-07-25-S2 | 10kg | short on VDDA line |
| 14-07-25-S4 | 5kg | biased to 40V (operated at 20V) |
 
---++ IV Scans

IV Scans on wafer and after processing

<img alt="Screen_Shot_2014-09-25_at_14.50.52.png" height="422" src="%PUBURL%/ATLAS/PUUKA/Connectivity/Screen_Shot_2014-09-25_at_14.50.52.png" width="613" />

---+ Characterisation
---+++ USBPix

Bump yield studies performed in August 2014 by Dan Smaranda and Richard Bates

[[%PUBURL%/ATLAS/PUUKA/Connectivity/21082014_Indium-DanSmaranda.pdf][21082014_Indium-DanSmaranda.pdf]]
---+++ RCE System

All modules tuned to and operated at 3000e threshold, 10ToT @ 16ke reference charge.
---+++++ Tuning

Module 14-07-24_S2:

Tune to 3000e, 10ToT @ 16ke

[[%PUBURL%/ATLAS/PUUKA/Connectivity/14-07-24_S2_3000eTuning.pptx][14-07-24_S2_3000eTuning.pptx]]

Module 14-07-25_S4:

Tune to 3000e, 10ToT @ 16ke

[[%PUBURL%/ATLAS/PUUKA/Connectivity/14-07-25_S4_3000eTuning.pptx][14-07-25_S4_3000eTuning.pptx]]
---+++++ Bump Yield Studies

Bump Yield assessed by performing Threshold Scans with and without sensor bias and performing source scans with Strontium-90 beta source and Americium-241 60keV gamma ray source.

[[%PUBURL%/ATLAS/PUUKA/Connectivity/Indium-Characterisation_0914.pptx][Indium-Characterisation_0914.pptx]]

---++ Bump yield results
| *Module* | *Bond Force* | *<p>Bump Yield</p> <p>(Sigma plot)</p>* | *<p>Bump Yield</p> <p>(Source Scans)</p>* |
| Indium1 | ? | 99.48% | 99.38% |
| 14-07-24-S2 | 20kg | 82.85% | 82.35% |
| 14-07-25-S4 | 5kg | 23.37% | 22.54% |
---++ Comments

<br />%COMMENT%
Topic revision: r1 - 2014-10-20 - RichardBates
ATLAS/PUUKA