The connective task has two main areas of work, TSV and flip-chip bonding development.

Flip-chip bonding at STFC-RAL

STFC/RAL are developing a fine pitched Indium flip-chip process. The samples first have an under bump metal (UBM) layer deposited upon them where the bump is to be grown. The UBM used to date is Ti/W, Ni, Au. The Ti/W is an adhesion layer to the Aluminium pad of the device. The nickel is the solderable metal layer and the Au is an oxidation barrier. The indium is deposited in a thermal reactor at RAL. The Indium is heated under vacuum and condenses on the sample that is held at a lower temperature. The samples can then be flip-chipped bonded. The flip-chip process is to work at room temperature or slightly elevated temperatures.

There is some worry that the Indium bumps require more pressure to form a bump than should be the case. One suggestion for this high pressure is that the gold used in the UBM is moving into the Indium and forming an Indium/Gold alloy which requires more force to deform. A SEM/FIB/EDX study of an Indium bump formed on a silicon substrate was performed in Glasgow to try and test the hypothesis that the gold had moved into the Indium. The report is found here:

The report's conclusion is that the gold does indeed appear to have migrated into the Indium bump.

First Indium Flip-chip bonded FE-I4

The first indium assembly wafer ID : VMB6NJH die 3

Sensor : CPII Live FE-I4 MPI Guard IBL

Indium_BumpYield_28032014.pptx: Bump Yield Studies March 2013

Indium Flip-Chipped Modules September 2014

Indium bumps require pressure only to make connections so no high temperatures are required to melt alloy, which reduces bowing effects.

Modules under test:

ID Bond ForceSorted ascending Comment
14-07-25-S4 5kg biased to 40V (operated at 20V)
14-07-25-S2 10kg short on VDDA line
14-07-24-S2 20kg biased to 40V

IV Scans

IV Scans on wafer and after processing




Bump yield studies performed in August 2014 by Dan Smaranda and Richard Bates


RCE System

All modules tuned to and operated at 3000e threshold, 10ToT @ 16ke reference charge.


Module 14-07-24_S2:

Tune to 3000e, 10ToT @ 16ke


Module 14-07-25_S4:

Tune to 3000e, 10ToT @ 16ke


Bump Yield Studies

Bump Yield assessed by performing Threshold Scans with and without sensor bias and performing source scans with Strontium-90 beta source and Americium-241 60keV gamma ray source.


Bump yield results

Module Bond Force

Bump Yield

(Sigma plot)

Bump Yield

(Source Scans)

Indium1 ? 99.48% 99.38%
14-07-24-S2 20kg 82.85% 82.35%
14-07-25-S4 5kg 23.37% 22.54%



Details of the TSV activity are given on the next page.

-- RichardBates - 2011-06-09

Topic attachments
I Attachment History Action Size Date Who Comment
PowerPointpptx 14-07-24_S2_3000eTuning.pptx r1 manage 159.3 K 2014-10-01 - 14:43 KateDoonan  
PowerPointpptx 14-07-25_S4_3000eTuning.pptx r1 manage 154.1 K 2014-10-01 - 14:43 KateDoonan  
PDFpdf 21082014_Indium-DanSmaranda.pdf r1 manage 598.7 K 2014-09-25 - 13:38 KateDoonan Bump Yield Studies by Richard Bates and Dan Smaranda 08/2014
PowerPointpptx Indium-Characterisation_0914.pptx r1 manage 580.0 K 2014-09-25 - 13:39 KateDoonan Bump yield studies by Kate Sexton
PowerPointpptx Indium_BumpYield_28032014.pptx r1 manage 636.5 K 2014-04-03 - 07:27 RichardBates Bump Yield Studies March 2013
Microsoft Word filedocx Report_on_SEM_Secondary_electron_images_and_EDX_measurements_on_In_bumps_from_RAL.docx r2 r1 manage 9890.4 K 2012-06-14 - 14:27 RichardBates Report on SEM for Indium bump from RAL
PNGpng Screen_Shot_2014-09-25_at_14.50.52.png r1 manage 156.1 K 2014-09-25 - 13:51 KateDoonan IV Characteristics of Modules before and after processing
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Topic revision: r8 - 2014-10-20 - RichardBates
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