Flip-chip bonding at STFC-RAL

STFC/RAL are developing a fine pitched Indium flip-chip process. The samples first have aunder bump metal (UBM) layer deposited upon them where the bump is to be grown. The UBM used to date is Ti/W, Ni, Au. The Ti/W is an adhesion layer to the Aluminium pad of the device. The nickel is the solderable metal layer and the Au is an oxidation barrier. The indium is deposited in a theraml reactor at RAL. The Indium is heated under vacuum and condenses on the sample that is held at a lower temperature. The samples can then be flip-chipped bonded. The flip-chip process is to work at room temperature or slightly elevated temperatures.

There is some worry that the Indium bumps require more pressure to form a bump than should be the case. One suggestion for this high pressure is that the gold used in the UBM is moving into the Indium and forming an Indium/Gold alloy which requires more force to deform. A SEM/FIB/EDX study of an Indium bump formed on a silicon substrate was performed in Glasgow to try and test the hypothesis that the gold had moved into the Indium. The report is found here:

• Report_on_SEM_Secondary_electron_images_and_EDX_measurements_on_In_bumps_from_RAL.docx: Report on SEM for Indium bump from RAL

The report's conclusion is that the gold does indeed appear to have migrated into the Indium bump.

Frist Indium Flip-chip bonded FE-I4

The first indium assembly wafer ID : VMB6NJH die 3

Sensor : CPII Live FE-I4 MPI Guard IBL

Indium_BumpYield_28032014.pptx: Bump Yield Studies March 2013

TSV

Details of the TSV activity are given on the next page.

-- RichardBates - 2011-06-09